As semiconductor device applications are expanded, a need for devices having a higher frequency response has arisen. For example, present generation bipolar devices typically have power-gain cut off frequencies (fmax) of about 350 GigaHertz (GHz). Consequently, the maximum frequency where bipolar devices provide a power gain greater than one is about 350 GHz. The maximum current gain cut-off frequency (fT) of such devices is similarly limited to around 300 GHz. Furthermore, the fmax of a transistor is an important device parameter to maximize and is especially relevant to RF applications.
The power-gain cut-off frequency of a bipolar device is influenced by a number of factors, particularly, the base resistance (RB), the capacitance between the collector and the base (CCB), and its ft. The fT is influenced by the transit time of carriers through emitter, base, and collector regions. Typically, the transit-time in the base and collector regions dominate the overall carrier transit-time, and should be minimized.
In order to maximize the fmax, the product of RB and CCB may be reduced, and the fT of the transistor may be increased. An increase in fT can be achieved by reducing the base transit-time as well as the collector transit-time. Traditional methods of improving the carrier transit time in the base layer include reducing the base layer thickness and increasing the Ge-induced built-in electric field. Similarly, the collector-base transit-time is traditionally addressed by reducing the thickness and resistance of the collector and by increasing the collector doping concentration (NC). However, increasing NC also increases the capacitance between the base and the collector and thus provides only a marginal benefit to fmax improvement.
Accordingly, traditional dimensional scaling approaches to improve fT or fmax can create other problems that reduce the benefits of such scaling approaches. Consequently, further improvements to increasing cut-off frequencies may require non-traditional techniques. It is well known in the art that carrier mobility can be improved by inducing strain (tensile or compressive) in a doped silicon material, thereby positively influencing the terminal characteristics of a device that is built thereof. For example, a process-induced tensile strain in the channel of an nFET can create improved electron mobility leading to higher saturation currents. In such situations, a tensile strain in the channel may be induced by applying a compressively strained nitride film close to the active region of the FET.